Today and in the next post, we will zoom in the core of Agilent digitizer technology mentioned by Pierre-François as another breakthrough: the development of in-house performance dedicated IC’s . Let us introduce you to our Analog & IC Design Manager, Daniel, who will talk about the clock-chip that was implemented on the M9703A.
Daniel, before we start, can you tell us a bit more of your background? I spent about half of my life doing Analog IC Design. I started as young engineer in a scope company designing FE, clock and Trigger circuits and moved to a large IC Manufacturer company doing Analog IC designs in the area of telecom, automotive and consumer electronic. I then got back in the measurement world dedicated my work to the design of digitizers. READ MORE
Why has Agilent decided to design a new clock circuit? Wouldn’t have been easier to buy and implement available IC’s?
Daniel: Agilent development’s team #1 objective is to guarantee that our high-speed digitizers reach high-level of performances. Therefore, when we cannot use or find available IC’s that respond to this demand, we design in-house dedicated full custom Analog IC. The clock chip is good example: Achieve very good Signal-to-Noise Ratio (SNR) performance has always been one of the top requirement priorities. However, with the development of higher and higher resolution analog to digital converters (ADC’s) and with the need of measuring higher and higher frequency signals, we realized that there were no circuits available on the market that could achieve such performance. Some available clock chip or ADC have built-in delay control, but while used this feature usually deteriorate the clock noise floor or jitter and then the SNR. Hence, we decided to create a complete new IC in order to respond to this need of performance for our high-speed digitizers.
A chart showing the SNR vs frequency & ADCs SNR at Nyquist showing the influence of the clock-chip and the Time Base on the SNR is available. Please request it by email and we will be happy to send it to you
Is the design of a clock circuit also the result of a design compromise like the analog FE is as explained by Neil in our last post? What are the main challenges and objectives behind it?
Daniel: In the design of clock-chip, the compromise is to compose with the different numerous analog circuits between maximum frequency of operation and noise in particular while implementing delay control function.Our target was to design a clock-chip with multiple clock output and delay control to drive multiple high resolutions ADC with the lowest noise floor or added-jitter as possible. In doing so, the M9703A, which is the 1st digitizer on which we implemented this new IC, achieves the unprecedented noise floor leading to a phase noise of -154 dBc/Hz at 2GHz and 100MHz offset even when using the whole delay control range.
Interested to get a figure showing the -154dBc/Hz phase noise at 2GHz and 100 MHz offset? Please send us this request by email.
We guess you are working closely with the others R&D groups. Is your development work continuously influenced by the others team’s requirements or the needs and definition of your design are clearly defined before you start working on it?
Daniel: Yes of course, we are working closely together and seating in the same space than the hardware and firmware design teams. This helps define the requirements and implement new concepts. Other R&D team members, but as well as sales and marketing people, are fully involved in the definition of our new ICs.
What are the main innovations that were developed with this new circuit? What can you tell us about them?
Daniel: One of the main innovations of our clock-chip is the new architecture design to control the phase and delay of the multiple clock outputs with no added jitter. This allows the best performances while interleaving ADCs and aligning channel sampling time.
What are the main added-values brought by the new clock circuit on the M9703A performances?
Daniel: The clock chip is a key block used in our Time Base mezzanine to provide ultra-low jitter clock to our four ADC mezzanines. The low added jitter of the clock-chip in the order of 25fs leads to a Time Base with an overall jitter of about 100fs. The on-chip delay adjustment allows us to align the sampling time between the ADC mezzanine and the multiple channel of M9703A.
What would be the graal of IC design on high-speed digitizers? Do you see room for others breakthrough innovations in the coming years in these field or rather continuous improvements based on your experience?
Daniel: The Monolithic ADC market is moving very fast in terms of performances. Of course there is always room for continuous improvement in clock-chips while trying to take the best of any new high resolution high speed ADC. The evolution of jitter in ADC is more like in saturation in order of 100fs but we can oversee improvement in terms of frequency and extended delay control ranges. One of the limitations we are always challenging with is board space and power dissipation which are limited in standard low cost package. Integration and trigger time resolution is another challenge that we also decided to respond to in our team as it will be covered in the next post. And as mentioned in the previous post, another key area where we can foresee huge improvement, is the ADC driver or signal amplifier with the venue and availability of new State of the Art IC technology.Tags: clock IC clock-chip share