The development and deployment of application specific signal processing algorithm are complete R&D projects. The in-house engineering resources are often not sufficient to allow fully dedicated engineers working on highly demanding application requirements. Therefore, Agilent high-speed data acquisition team (HSADC) has partnered with research institutes such as for example the Microelectronics Institute of FHNW University of Applied Sciences and Arts Northwestern Switzerland. In this context, we have the opportunity today to introduce you to Mr. Dino Zardet, research fellow at this institute who we invited to talk about his work and relationship with Agilent HSADC. DISCOVER HIS INTERVIEW
HSADC: Please shortly introduce yourself and describe what you do and what are your specializations?
Dino Zardet (DZ): I work as digital design engineer with FPGAs, ASICs and embedded systems. At the moment, I am working on a project where we develop a fast Fourier transform (FFT) algorithm to be deployed on Agilent digitizers which will be used for radio astronomy applications. I am also working on generating scan test pattern for the digital part of a customer mixed-signal ASIC to guarantee a high test coverage for the manufacturing test of the chip.IF YOU WOULD LIKE TO LEARN MORE ABOUT THIS FUTURE FAST FOURIER TRANSFORM OPTION: CONTACT US
HSADC: Since when do you partnership with Agilent ? How have you learned form each other?
DZ: Actually we worked already in 2004 and 2007 with Acqiris SA (before it turned to Agilent) where we also developed an FFT IP for AC240 digitizer (U1082A). We were one of the first users who built their own IP on this system. It was great because both Agilent and us were able to improve our design in order to get a robust framework for future projects.
HSADC: Can we say you work as a third party for Agilent? How would you define your business relationship?
DZ: No I wouldn’t say that, Agilent is more like a project partner for us together with the Institute of Astronomy of ETH Zurich and Institute of Applied Physics of University of Bern.
HSADC: What are the Agilent tools you are using for this project?
DZ: We are mainly using the FPGA development kit (FDK) provided by Agilent including the design tools powered by Mentor Graphics. With this tool, we are able to develop our user design (firmware), simulate its correct function and finally generate a bitfile for the FPGA using a semi-automatic building script.
HSADC: What are the main advantages of the FPGA development kit as a user?
DZ: Basically the users are able to design their IP core in the framework with AXI4 interfaces from the design entry up to the final bitfile. The FDK enables us to insert our function into the overall framework of the Agilent digitizers. It thus isolates our user core functionality from all nasty details of the interfaces and reduces dramatically the work to be done in order to integrate the function into the digitizers. Thanks to the FDK, the user receives a verified environment,including the FPGA design flow tools and their set up, so he can concentrate on designing and verifying his user functionality.
HSADC: In what it helps you in your work? Can you think of others applications where these tools could be useful?
DZ: The tools are dedicated to IP core design for Agilent high-speed digitizers. So we were able to work quickly and efficiently on the development of our own firmware cores and through the whole backend flow. If you want to deploy dedicated signal processing firmware, it’s the way to go.
We could also potentially leverage from this project in the future. Our Institute is now very well placed for similar tasks of designing user cores on Agilent’s digitizers’ platforms for other end-users willing to delegate similar projects to research and development partners.
HSADC: If you had the keys to high-speed ADC and signal processing technology evolution. What would be the key improvements you would like to have in the next 10 years and why?
DZ: I would like to get larger FPGAs with higher speed in order to have more functionality space and less timing problems.Tags: FFT fpga development kit share