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Home » news » Best in test #5: what do we mean by synchronization?

Best in test #5: what do we mean by synchronization?

EduardoLet’s continue our journey into the technology breakthroughs realized during the development of the Best in Test award Winner in signal analyzer the M9703A. Let’s meet with Eduardo who will take us on a tour around synchronization.  

Eduardo, can you briefly describe your background before you joined Agilent?

I have spent most of my career working as digital designer on FPGAs  and ASICs. READ MORE 

 After finishing my Masters, I joined CERN (European Organization for Nuclear Research). Firstly, I was in charge of the FPGA optimization of SRAM controls in an existing data acquisition board based on VME for high energy physics applications. Secondly, I was responsible for the design and development of the full digital circuitry (data signal processing and digital interface) in a mixed mode ASIC to scope Time Projection Chamber detectors. The work was defended as part of my PhD at Universidad Politecnica de Valencia (Spain).  I then  joined Agilent as part of the FPGA design team and I have been involved in different projects; for instance, the U1084 zero suppression scheme, the trigger circuitry, high-speed digitizer architecture, multi-board synchronization described here… among others.

How would you define synchronization and in what type of applications, synchronization is a key attribute for a digitizer?

The term synchronization is quite general; we usually say that two systems are synchronous when they run at the same reference clock. The M9703A presents a multi-channel multi-board scalable architecture that provides not only synchronous sampling over multiple channels located on several boards but also synchronous processing over multiple boards.

The synchronous sampling assures that each acquisition channel is sampled at the same absolute time. While the synchronous processing guarantees that all the processing algorithms are running simultaneously on the same set of samples (trigger information is included in real time). The M9703A synchronous sampling is possible due to in-house ASICs while the synchronous processing over multiple boards is possible due to the firmware flexibility and precise calibration algorithms.

Currently, we are able to scale-up seamlessly multiple boards to create 40 synchronous processing channels (High-speed digitizers, DDCs or any other processing algorithm) using the Agilent’s M9505A chassis. This is a tremendous gain for a diverse range of applications as: phased array radars, radiographic facilities, fusion research, particle physics…

What are the key R&D challenges that are lying behind the channels’ synchronization of a digitizer like the M9703A?

It’s not possible to synchronously distribute  GHz range sampling clocks from one board to another without affecting either its quality or its relative phase matching. So, the challenge is to provide all the necessary hardware and software elements to assure synchronous sampling and synchronous processing in multiple “asynchronous” boards. It is also important that these elements are part of our M9703A and the chassis to avoid using any additional hardware.  For instance, this solution employs some AXIe backplane resources, such as the common AXIe 100MHz reference clock and AXIe Local Bus. 


M9703A block diagram




















Do you think that the synchronization across channels on a digitizer can still be improved?

As explained by Nicolas (Best in test #4), the trace positioning standard deviation in all channels individually is 12 ps rms. If we consider all channels in a single board, the standard deviation is ~13.5 ps rms. And the first tests have shown that, if we consider all channels in multiple boards, the standard deviation is ~15 ps rms. These are great results for such a scalable system!! 

The only limitation (in decreasing the standard deviation) is the accuracy of the reference clock distributed through the backplane which introduce a fixed inter-channel skew. Nevertheless, this is not an issue in the M9703A, because we provide channel deskewing controls. These controls can further improve the inter-channel skew by deploying a system calibration including all mismatches (even including external cables if required).

What would it bring to the big physics experiments?

We know that physics experiments require more and more high-speed synchronized channels with fast data acquisition to accurately capture experimental events. We therefore present a real solution to facilitate the tedious and complex task of synchronizing multiple channels. On top of that, the M9703 provides the possibility of including custom user-designed processing algorithms in these multiple channels (for more info contact us). So, the client will “only” focus on the processing algorithms and will profit from the Agilent Technologies multi-channel infrastructure. 

And how do you see it in the future? 

In the near future, we would like to test our solution in a chassis with greater number of slots and potentially with lower backplane skew. We expect to have around 100 channels with synchronous sampling and synchronous processing in a single chassis. But, this is not the end… a new challenge will come with the synchronization across several chassis. This is a new challenge that personally I am quite excited about!!



About Benedetta Viti

Benedetta is a PR & Web Editor. She is the key player behind the blog High-Speed ADC, willing to know more about the people behind the products. She holds a Bachelor in Languages and a Master in International Marketing.

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