Following the win of the T&M Award “Best in Test” in the category signal analyzer of our latest product, the 12-bit 8 channels AXIe digitizer, we will take you during the next 2 weeks on a tour of the technology breakthroughs that needed to be developed in order to release this new digitizer. It should also help you understand how the Agilent high-speed ADC technology team responds to the highest demands in terms of performances, reliability and time to market. It was obvious to us to start with the interview of our AXIe R&D project manager, Pierre-François. READ MORE
Pierre-François, tell us a little bit about your technical background and history.
Pierre-François (PF): I have a strong technical background in electronics design ranging from high-reliability embedded designs for Defense and Aerospace applications to state-of-the-art FPGA based architectures. As a hardware design engineer I have been involved in many area including digital processing, high speed serial data transmission, high speed digital design within FPGA and obviously high speed digitizer design in several form factors.
Pierre-François, as the M9703A project manager how did you feel when you learnt that your product won the “ BEST in Test” award in the category signal analyzer?
PF: I’m very proud of all the work that has been delivered by the cross-functional team: It was the most complex digitizer design we ever carried out but it was really exciting to develop a new product in an emerging AXIe form factor standard.
Did the fact that this digitizer is based on AXIe, the new modular industry’s open factor, influence your approach and design of the product architecture compared to other products?
PF: Yes, it did definitively. AXIe is basically a measurement-oriented standard layer based on the well-established ATCA standard. It offers both a wide PCB area that let us implement 4 front-end analog mezzanines on a single carrier board and enough power efficiently drawn from a single power rail. The AXIe infrastructure provides also convenient triggering schemes and reference clock distribution across multiple boards and the AXIe Local bus has been used to provide a unique data processing scalability and synchronization over multiple adjacent boards.
We hear that the M9703A implements a number of technology breakthroughs. Can you tell us a little bit about what they are? Which ones are you particularly proud of?
PF: This is correct: As part of this new platform we have integrated a number of breakthrough technologies such as an innovative front-end architecture, an enhanced clocking scheme based on an in-house developed IC that delivers clean sampling clock distribution with unmatched added-data jitter performance, a very precise trigger positioning also based on a custom IP chip and a multi-channel multi-board scalable architecture providing phase-matched channels with de-skewing capabilities. I’m very proud of our multi-channel multi-board scalable architecture that provides not only synchronous sampling over multiple channels located on several boards but also synchronous processing over multiple boards as required for example on multiple DDC channels applications. The M9703 provides a true advantage for multi-channels applications and having the ability to scale-up seamlessly multiple boards to create a 40 synchronous processing channels system is really exiting.
For you, what are the key performance and/or features a potential user should look at when considering a high-speed digitizer? How is the M9703A situated in this context?
PF: The analog data conversion performances are of course of primary concerns, but the user should also pay attention to the some details such as the offset range capability, the proposed bandwidth and especially the true performances over the full bandwidth (not only limited as low Fin frequency). The user shall also look at the proposed clocking schemes and their related phase noise performances because the quality of the clock distribution is directly impacting the data conversion performances at high input frequencies .In addition for multi-channel applications the channel phase-matching or channel deskewing capability is of course of significant concern. The M9703A addresses the points above by especially providing consistent data conversion performances over its large input bandwidth and supporting an external clocking scheme that only adds 25fs of added jitter to the user clocking source.
We guess you are now working on new projects. We understand that they are certainly still quite confidential but could you provide some indications to our readers?
PF: With the M9703A, we’ve built the ground foundation for our AXIe digitizer family. We are now looking at providing additional firmware features such as enabling the Customer to program his own firmware within our digitizer platform and to extend the product portfolio with other data conversion characteristics…
If you were projected in 10 years time, how do you think the high-speed digitizer technology will have evolved and on what types of projects do you imagine working on?
PF: Over the last decade the technology rapidly evolved from 8-bit multi GS/S ADC to 12-bit multi GS/s ones and from the first simple FPGA equipped with a couple of MGT to very large with dozen of MGT. Thus I imagine working on multi GS/s16-bit digitizer with high-end FPGA equipped with multiple 100Gb/s transceivers…
Thanks for your time and congratulations again for the Award.Tags: m9703a share