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Simultaneous Acquisition and Readout (SAR) application

Today’s article is an application brief on simultaneous acquisition and readout using the U5340A FPGA development kit.  A complete example application note can be provided upon request and it includes the HDL source code, a building script and the control application for the U5303A and M9703A products so that the user can speed up the development and customize easily the design to adapt it to its own need.

Introduction

Numerous test scenarios require gap-free or continuous acquisition of digitized data for minutes, hours or days. A variety of system configurations will enable effective implementation of such applications along with the required processing and analysis of the captured data. One very common and effective arrangement  is the implementation of a FIFO-like scheme in which the data are stored  and read simultaneously to/from an on board buffer.

SAR figure 1

 

Figure 1 visually illustrates the concept of simultaneous acquisition and readout (SAR) versus a standard acquisition and readout scheme for a multi records acquisition.

From an application perspective is not relevant if the data are captured as a single record resulting from a unique trigger or as multiple records resulting from multiple events as long as the following two requirements are satisfied:

  1. “Acquisition Data Rate” < “Readout Data Rate”
  2. On board Buffer size > “Acquisition Data Rate” x “Maximum System Latency” 

The first condition is necessary to guarantee the gap-free scenario and the second condition is necessary to compensate the unavoidable system latencies due to the OS pre-emption. Example applications that require SAR implementation include signal monitoring, software defined radio, microwave astrophysics, atmospheric research, pulsed radar and telemetry systems, analysis of particle-beam steering in cyclotron accelerators, medical imaging.

Data reduction and SAR with the U5340A FDK

When the volume of the digitized data is too high for the host system a data reduction treatment needs to be applied to the incoming data before transferring them to the storage media. Most of the Agilent Technologies modular digitizer products like the U5303A and M9703A adopt a FPGA based architecture where each processing channel contains a Digital Processing Unit (DPU) making them ideal to host User-Defined Core implementing such custom real time processing. That is where the U5340A FPGA Development Kit (FDK) comes into play by providing a complete development framework for the supported Agilent modular data converter platforms.

The U5340A-FDK allows the programmer to directly access the underlying hardware resources and the FPGA’s processing capabilities in an easy and effective manner hence allowing the implementation of custom Real-Time processing functions such as FFT, Digital Down Conversion (DDC), Peak detection etc. along with the SAR mechanism.

Conclusion

Implementing a SAR application using the U5340A FDK in one of the supported digitizer platforms is straight forward. Interested? As mentioned, a complete example application note can be provided upon request and it includes the HDL source code, a building script and the control application for the U5303A and M9703A products so that the user can speed up the development and customize easily the design to adapt it to its own need. 

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About Benedetta Viti

Benedetta is a PR & Web Editor. She is the key player behind the blog High-Speed ADC, willing to know more about the people behind the products. She holds a Bachelor in Languages and a Master in International Marketing.

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